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1 ltc4244/LTC4244-1 42441f applicatio s u features typical applicatio u descriptio u n controls C12v, 3.3v, 5v and 12v supplies n 14.4v absolute maximum rating for 12v in and C12v in input pins n insensitive to supply voltage transients n adjustable foldback current limit with circuit breaker n local_pci_rst# logic on-chip n precharge output biases i/o pins during card insertion and extraction n LTC4244-1 designed for applications without C12v n available in 20-lead narrow ssop package , ltc and lt are registered trademarks of linear technology corporation. n hot board insertion into compactpci bus the ltc ? 4244/LTC4244-1 are hot swap tm controllers that allow a board to be safely inserted into and removed from a compactpci tm bus slot. external n-channel transistors control the 5v and 3.3v supplies while on-chip switches control the 12v supplies. the 3.3v and 5v supplies can be ramped up at an adjustable rate. electronic circuit breakers protect all four supplies against overcurrent faults. after the power-up cycle is complete, the timer pin capacitor serves as auxiliary v cc allowing the ltc4244/ LTC4244-1 to function without interruption in the pres- ence of voltage spikes on the 12v in supply. the pwrgd output indicates when all four supplies are within toler- ance. the off/on pin is used to cycle board power or reset the circuit breaker. the precharge output can be used to bias the bus i/o pins during card insertion and extrac- tion. pci_rst# is combined on-chip with healthy# in order to generate local_pci_rst#. 3.3v in 12v in 12v out v eein off/on z4 5v in r4 10 c load(5vout) v out 5v 5a v out 3.3v 7a r5 1k c1 0.33 f r3 10 r1 0.005 r2 0.007 q1 irf7457 q2 irf7457 3.3v out 3.3v sense gnd precharge 5v in 5v sense drive r9 24 1v 10% q3 mmbt2222a c3 4.7nf v in 3.3v 4244 f01 ltc4244 gate 5v out + c load(3.3vout) + v out 12v 500ma c load(12vout) + v eeout timer resetout i/o #1 i/o #128 v eeout C12v 100ma v out 3.3v c load(veeout) c2 0.082 f + z3 z2 z1 r17 10k 3.3v in r22 2.7 c9 0.01 f per power pin c7 0.01 f c8 0.01 f per power pin r21 1.8 r19 1k fault pwrgd resetin r18 10k r20 1.2k r16 1 c6 0.01 f r8 1k r7 12 r6 10k r10 18 r11 10k r13 10 r14 10 ? ? ? ? ? ? ? ? ? r12 10k c5 0.01 f r15 1 c4 0.01 f i/o data line 1 i/o data line 128 z1, z2: smaj12a z3, z4: smaj5.0a i/o pin 128 reset# pci bridge chip i/o pin 1 ground pci_rst# local_pci_rst# healthy# long v(i/o) bd_sel# C12v 12v long 3.3v long 5v 3.3v 5v figure 1. typical compact pci application hot swap is a trademark of linear technology corporation. compactpci is a trademark of the pci industrial computer manufacturers group. rugged, compactpci bus hot swap controllers
2 ltc4244/LTC4244-1 42441f gn package 20-lead plastic ssop 1 2 3 4 5 6 7 8 9 10 top view 20 19 18 17 16 15 14 13 12 11 12v in v eein 5v out timer off/on fault pwrgd gnd resetin resetout 12v out v eeout 3.3v out 3.3v in 3.3v sense gate 5v sense 5v in precharge drive (notes 1, 2, 3) supply voltages 12v in ................................................................ 14.4v v eein .............................................................. C14.4v input voltages (off/on, resetin) ........C 0.3v to 13.5v output voltages (fault, pwrgd, resetout) ...........................................................C 0.3v to 13.5v analog voltages and currents 5v out , drive, 5v in , 3.3v sense , 3.3v in , 3.3v out , 5v sense ...........................................................C 0.3v to 13.5v precharge, gate ....................................... 20ma v eeout ................................................ C14.4v to 0.3v timer, 12v out ........................................... C 0.3v to 14.4v operation temperature range ltc4244c/ltc4244c-1 ........................... 0 c to 70 c ltc4244i/ltc4244i-1 ........................ C 40 c to 85 c storage temperature range ................. C 65 c to 150 c lead temperature (soldering, 10 sec).................. 300 c order part number ltc4244cgn ltc4244cgn-1 ltc4244ign ltc4244ign-1 t jmax = 140 c, q ja = 135 c/ w symbol parameter conditions min typ max units i dd v 12vin supply current off/on = 0v l 410 ma v lko undervoltage lockout 12v in , ramping down l 8 9 10 v 5v in , ramping down l 4 4.25 4.5 v 3.3v in , ramping down l 2.25 2.5 2.75 v v eein , ramping up (ltc4244 only) l C8.25 C9.25 C10.25 v timer, ramping down, v 12vin = 6v l 8.25 9.25 10.25 v v fb foldback current limit voltage v fb = (v 5vin C v 5vsense ), v 5vout = 0v, timer = 0v l 11 16 21 mv v fb = (v 5vin C v 5vsense ), v 5vout = 3v, timer = 0v l 46 51 56 mv v fb = (v 3.3vin C v 3.3vsense ), v 3.3vout = 0v, timer = 0v l 11 16 21 mv v fb = (v 3.3vin C v 3.3vsense ), v 3.3vout = 2v, timer = 0v l 46 51 56 mv v cb circuit breaker trip voltage v cb = (v 5vin C v 5vsense ), timer = float l 45 52 57 mv v cb = (v 3.3vin C v 3.3vsense ), timer = float l 45 52 57 mv t oc overcurrent fault response time (v 5vin C v 5vsense ) = 100mv, timer = float l 17 25 35 m s (v 3.3vin C v 3.3vsense ) = 100mv, timer = float l 17 25 35 m s i gate(up) gate pin output current off/on = 0v, v gate = 2v, timer = 0v l C20 C67 C100 m a i gate(dn) v gate = 5v, off/on = 4v l 20 60 100 m a i gate(fault) off/on = 0v, v gate = 2v, timer = float, fault = 0v l 4 8 16 ma d v gate external gate voltage d v gate = (v 12vin C v gate ), i gate = C1 m a l 0.6 1 v d v 12v internal switch voltage drop d v 12v = (v 12vin C v 12vout ), i = 500ma l 225 600 mv d v vee d v vee = (v eeout C v eein ), i ee = 100ma l 110 250 mv consult ltc marketing for parts specified with wider operating temperature ranges. absolute axi u rati gs w ww u package/order i for atio uu w electrical characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. v 12vin = 12v, v eein = C12v, v 3.3vin = 3.3v, v 5vin = 5v, unless otherwise noted.
3 ltc4244/LTC4244-1 42441f symbol parameter conditions min typ max units i cl current foldback 12v in = 12v, 12v out = 0v, timer = 0v l C100 C360 C1000 ma 12v in = 12v, 12v out = 10v, timer = 0v l C550 C850 C1500 ma v eein = C12v, v eeout = 0v, timer = 0v l 50 225 350 ma v eein = C12v, v eeout = C10v, timer = 0v l 350 610 870 ma t ts thermal shutdown temperature junction temperature, ramping up 150 c v th power good threshold voltage 12v out , ramping down l 10.8 11.1 11.4 v 5v out , ramping down l 4.50 4.61 4.75 v 3.3v out , ramping down l 2.80 2.90 3.00 v v eeout , ramping up, ltc4244 only l C10.8 C11.1 C11.4 v v il logic input low voltage off/on, resetin, fault l 0.8 v v ih logic input high voltage off/on, resetin, fault l 2v i in off/on, resetin input current off/on, resetin = 0v l 10 m a off/on, resetin = 12v l 10 m a resetout, fault leakage resetout, fault = 5v, off/on = 0v, resetin = 3.3v l 10 m a current pwrgd output current pwrgd = 5v, off/on = 4v l 10 m a 5v sense input current 5v sense = 5v, 5v out = 0v l 57 100 m a 3.3v sense input current 3.3v sense = 3.3v, 3.3v out = 0v l 56 100 m a 5v in input current 5v in = 5v, timer = 0v l 0.8 1.5 ma 3.3v in input current 3.3v in = 3.3v, timer = float l 510 700 m a 3.3v in = 3.3v, timer = 0v l 400 550 m a 5v out input current 5v out = 5v, off/on = 0v, timer = 0v l 107 200 m a 3.3v out input current 3.3v out = 3.3v, off/on = 0v, timer = 0v l 170 300 m a precharge input current v precharge = 1v l 0.1 10 m a i timer timer pin current off/on = 0v, v timer = 0v l 16 21 26 m a off/on = 5v, v timer = 5v l 25 45 70 ma v timer timer threshold voltage timer_hi, (v 12vin C v timer ), fault = 0v, ramping up l 1.3 1.6 1.9 v timer_lo, v timer , ramping down l 0.5 0.8 1.1 v d v timer external timer voltage d v timer = (v 12vin C v timer ), i timer = C1 m a l 1v r dis 12v out discharge resistance off/on = 4v l 440 1000 w 5v out discharge resistance off/on = 4v l 200 500 w 3.3v out discharge resistance off/on = 4v l 200 500 w v eeout discharge resistance off/on = 4v l 390 1000 w v ol output low voltage pwrgd, resetout, fault, i = 1ma l 0.4 v v pxg precharge reference voltage v drive = 2v l 0.95 1 1.05 v electrical characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. v 12vin = 12v, v eein = C12v, v 3.3vin = 3.3v, v 5vin = 5v, unless otherwise noted. note 1: absolute maximum ratings are those values beyond which the life of a device may be impaired. note 2: all currents into device pins are positive; all currents out of device pins are negative. all voltages are referenced to ground unless otherwise specified. note 3: the 12v in and v eein pins will withstand transient surges up to 15v, respectively, upon hot insertion.
4 ltc4244/LTC4244-1 42441f 3.3v and 5v current foldback profile 12v out current vs 12v out voltage v eeout current vs v eeout voltage 12v foldback current limit vs temperature v ee foldback current limit vs temperature 12v internal switch voltage drop vs temperature v ee internal switch voltage drop vs temperature 5v in foldback current limit voltage vs temperature 3.3v in foldback current limit voltage vs temperature typical perfor a ce characteristics uw voltage (v) 0 voltage (mv) 1 3.3v 5v 234 4244 g01 5 60 50 40 30 20 10 0 voltage (v) 0 current (a) 246 10 8 4244 g02 12 1.0 0.9 0.7 0.5 0.3 0.8 0.6 0.4 0.2 0.1 0 voltage (v) 0 current (a) C2 C4 C6 C10 C8 4244 g03 C12 C0.6 C0.5 C0.3 C0.4 C0.2 C0.1 0 temperature ( c) C50 current (a) C25 0 25 75 50 4244 g04 100 0.9 0.8 0.7 0.6 0.5 0.3 0.4 0.2 0.1 0 12v out = 10v 12v out = 0v temperature ( c) C50 current (a) C25 0 25 75 50 4244 g05 100 0.6 0.5 0.3 0.4 0.2 0.1 0 v eeout = 10v v eeout = 0v temperature ( c) C50 voltage (v) C25 0 25 75 50 4244 g06 100 0.30 0.25 0.15 0.20 0.10 0.05 0 i 12vout = 550ma temperature ( c) C50 voltage (v) C25 0 25 75 50 4244 g07 100 0.14 0.12 0.10 0.06 0.08 0.04 0.02 0 i veein = 100ma temperature ( c) C50 voltage (mv) C25 0 25 75 50 4244 g09 100 60 50 30 40 20 10 0 3.3v out = 2v 3.3v out = 0v temperature ( c) C50 voltage (mv) C25 0 25 75 50 4244 g08 100 60 50 30 40 20 10 0 5v out = 3v 5v out = 0v
5 ltc4244/LTC4244-1 42441f 3.3v in and 5v in circuit breaker trip voltage vs temperature 3.3v in and 5v in circuit breaker trip filter time vs temperature 12v in supply current vs temperature 12v in undervoltage lockout vs temperature v eein undervoltage lockout vs temperature 5v in undervoltage lockout vs temperature 3.3v in undervoltage lockout vs temperature 12v out powergood threshold voltage vs temperature v eein powergood threshold voltage vs temperature typical perfor a ce characteristics uw temperature ( c) C50 voltage (mv) C25 0 25 75 50 4244 g10 100 52.0 51.6 51.8 51.4 51.2 51.0 50.6 50.8 50.4 50.2 50.0 5v in 3.3v in temperature ( c) C50 time ( s) C25 0 25 75 50 4244 g11 100 25.0 24.5 24.0 23.0 23.5 22.5 22.0 21.5 temperature ( c) C50 current (ma) C25 0 25 75 50 4244 g12 100 3.94 3.93 3.92 3.90 3.91 3.89 3.88 3.87 temperature ( c) C50 voltage (v) C25 0 25 75 50 4244 g13 100 9.30 9.25 9.20 9.10 9.15 9.05 9.00 8.95 ramping-up ramping-down temperature ( c) C50 voltage (v) C25 0 25 75 50 4244 g14 100 C9.22 C9.24 C9.26 C9.30 C9.28 C9.32 C9.34 C9.36 ramping-up ramping-down temperature ( c) C50 voltage (v) C25 0 25 75 50 4244 g15 100 4.34 4.32 4.30 4.26 4.28 4.24 4.22 4.20 ramping-up ramping-down temperature ( c) C50 voltage (v) C25 0 25 75 50 4244 g16 100 2.54 2.53 2.52 2.50 2.51 2.49 2.48 2.45 2.46 2.47 ramping-up ramping-down temperature ( c) C50 voltage (v) C25 0 25 75 50 4244 g17 100 11.090 11.085 11.080 11.070 11.075 11.065 11.060 11.055 temperature ( c) C50 voltage (v) C25 0 25 75 50 4244 g18 100 C11.050 C11.055 C11.060 C11.070 C11.065 C11.075 C11.080
6 ltc4244/LTC4244-1 42441f 5v out powergood threshold voltage vs temperature 3.3v out powergood threshold voltage vs temperature gate pin current vs temperature gate pin fault current vs temperature timer pin on current vs temperature timer pin off current vs temperature timer threshold voltage vs temperature discharge resistance vs temperature v ol vs temperature typical perfor a ce characteristics uw temperature ( c) C50 voltage (v) C25 0 25 75 50 4244 g19 100 4.603 4.602 4.601 4.599 4.600 4.598 4.597 4.594 4.595 4.596 temperature ( c) C50 voltage (v) C25 0 25 75 50 4244 g20 100 2.902 2.901 2.900 2.898 2.899 2.897 2.896 2.894 2.895 temperature ( c) C50 current ( a) C25 0 25 75 50 4244 g21 100 80 60 40 0 20 C20 C40 C80 C60 off/on = 0v off/on = 4v temperature ( c) C50 current (ma) C25 0 25 75 50 4244 g22 100 16 14 12 8 10 6 4 0 2 fault = 0v temperature ( c) C50 current ( a) C25 0 25 75 50 4244 g23 100 20.30 20.25 20.20 20.15 20.10 20.05 temperature ( c) C50 current (ma) C25 0 25 75 50 4244 g24 100 60 50 40 20 30 10 0 temperature ( c) C50 voltage (v) C25 0 25 75 50 4244 g25 100 1.66 1.64 1.62 1.60 1.58 1.56 1.52 1.54 1.50 1.48 1.46 12v in C v timer temperature ( c) C50 resistance ( ) C25 0 25 75 50 4244 g26 100 700 600 500 300 400 200 100 0 12v out v eeout 3.3v out 5v out temperature ( c) C50 resistance ( ) C25 0 25 75 50 4244 g27 100 250 150 200 100 50 0 resetout pwrgd fault
7 ltc4244/LTC4244-1 42441f uu u pi fu ctio s 12v in (pin 1): 12v supply input. a 0.5 w switch is con- nected between 12v in and 12v out with a foldback current limit. an undervoltage lockout circuit prevents the switches from turning on while the 12v in pin voltage is less than 9v. 12v in also provides power to the ltc4244s internal v cc node. v eein (pin 2): C12v supply input. a 1 w switch is con- nected between v eein and v eeout with a foldback current limit. an undervoltage lockout circuit prevents the switches from turning on while the v eein pin voltage is greater than C9.25v. the v eein undervoltage lockout function is dis- abled for the LTC4244-1. 5v out (pin 3): 5v output sense. the pwrgd pin will not pull low until the 5v out pin voltage exceeds 4.61v. a 200 w active pull-down discharges 5v out to ground when the power switches are turned off. timer (pin 4): current fault inhibit timing input and auxiliary v cc . connect a capacitor from timer to gnd. when the ltc4244 is turned on, a 21 m a pull-up current source is connected to timer. current limit faults will be ignored until the voltage at the timer pin rises to within 1.6v of 12v in . after the timer pin has completed ramp- ing up, the timer capacitor serves as an auxiliary charge reservoir for v cc in the event the 12v in pin voltage momentarily drops below the undervoltage lockout thresh- old voltage. when the ltc4244 is turned off (off/on > 2v), the timer pin is pulled down to gnd. after the timer pin voltage drops to within 0.8v of gnd, the timer latch is reset and the part is ready for another power cycle. off/on (pin 5): digital input. connect the cpci bd_sel# signal to the off/on pin. when the off/on pin is pulled low, the gate pin is pulled high by a 67 m a current source and the internal 12v and C12v switches are turned on. when the off/on pin is pulled high, the gate pin will be pulled to ground by a 60 m a current source and the 12v and C12v switches turn off. fault (pin 6): open-drain digital i/o. fault is pulled low when a current limit fault is detected. current limit faults are ignored until the voltage at the timer pin is within 1.6v of 12v in . once the timer cycle is complete, fault will pull low and the ltc4244 latches off in the event of an overcurrent fault. the part will remain in the latched off state until the off/on pin is cycled high then low. forcing the fault pin low with an external pull-down will cause the part to latch into the off state after a 25 m s deglitching time. pwrgd (pin 7): open-drain digital power good output. connect the cpci healthy# signal to the pwrgd pin. pwrgd remains low while v 12vout 3 11.1v, v 3.3vout 3 2.9v, v 5vout 3 4.61v, and v eeout C11.1v. when any of the supplies falls below its power good threshold voltage, pwrgd will go high after a 14 m s deglitching time. gnd (pin 8): device ground. resetin (pin 9): digital input. connect the cpci pci_rst# signal to the resetin pin. pulling the resetin pin low will cause resetout to pull low. resetout will also pull low when pwrgd is high.
8 ltc4244/LTC4244-1 42441f resetout (pin 10): open-drain digital output. connect the cpci_local_rst# signal to the resetout pin. resetout is the logical combination of the resetin and pwrgd. drive (pin 11): precharge base drive output. provides base drive for an external npn emitter-follower that in turn biases the precharge node. precharge (pin 12): precharge monitor input. an inter- nal error amplifier servos the drive pin voltage to keep the precharge node at 1v. see applications information for generating voltages other than 1v. if not used, tie the precharge pin to ground. 5v in (pin 13): 5v supply sense input. an undervoltage lockout circuit prevents the switches from turning on when the voltage at the 5v in pin is less than 4.25v. 5v sense (pin 14): 5v current limit sense. with a sense resistor placed in the supply path between 5v in and 5v sense , the gate pin voltage will be adjusted to maintain a constant 51mv across the sense resistor and a constant current through the switch while the timer pin is low. a foldback feature makes the current limit decrease as the voltage at the 5v out pin approaches gnd. when the timer pin is high, the circuit breaker function is enabled. if the voltage across the sense resistor exceeds 52mv, the circuit breaker is tripped after a 25 m s time delay. in the event of a short-circuit or large overcurrent transient condition, the gate pin voltage will be adjusted to main- tain a constant 150mv across the sense resistor and a constant current through the switch. gate (pin 15): high side gate drive for the external 3.3v and 5v n-channel pass transistors. an external series rc network is required for current limit loop compensation and setting the minimum ramp-up time. during power-up, the slope of the voltage rise at the gate is set by the 67 m a current source connected through a schottky diode to 12v in and the external capacitor connected to gnd (c1 in figure 1) or by the 3.3v or 5v current limit and the bulk capacitance in the 3.3v out or 5v out supply lines. during power down, the slew rate of the gate voltage is set by the 60 m a current source connected to gnd and the external gate capacitor (c1 in figure 1). the voltage at the gate pin will be modulated to maintain a constant current when either the 5v or 3.3v supplies go into current limit. in the event of an overcurrent fault, the gate pin is immediately pulled to gnd. 3.3v sense (pin 16): 3.3v current limit sense. with a sense resistor placed in the supply path between 3.3v in and 3.3v sense , the gate pin voltage will be adjusted to maintain a constant 51mv across the sense resistor and a constant current through the switch while the timer pin is low. a foldback feature makes the current limit decrease as the voltage at the 3.3v out pin approaches gnd. when the timer pin is high, the circuit breaker function is enabled. if the voltage across the sense resistor exceeds 52mv, the circuit breaker is tripped after a 25 m s time delay. in the event of a short-circuit or large overcurrent transient condition, the gate pin voltage will be adjusted to main- tain a constant 150mv across the sense resistor and a constant current through the switch. if no 3.3v input supply is available, short the 3.3v sense pin to the 5v in pin. uu u pi fu ctio s
9 ltc4244/LTC4244-1 42441f 3.3v in (pin 17): 3.3v supply sense input. an undervolt- age lockout circuit prevents the switches from turning on when the voltage at the 3.3v in pin is less than 2.5v. if no 3.3v input supply is available, short the 3.3v in pin to the 5v in pin. 3.3v out (pin 18): analog input used to monitor the 3.3v output supply voltage. the pwrgd pin cannot pull low until the 3.3v out pin voltage exceeds 2.9v. if no 3.3v input supply is available, tie the 3.3v out pin to the 5v out pin. a 200 w active pull-down discharges 3.3v out to ground when the power switches are turned off. uu u pi fu ctio s v eeout (pin 19): -12v supply output. a 1 w switch is connected between v eein and v eeout . v eeout must be less than C11.1v before the pwrgd pin pulls low. the v eeout power good comparator is disabled for the LTC4244-1. a 390 w active pull-up discharges v eeout to ground when the power switches are turned off. 12v out (pin 20): 12v supply output. a 0.5 w switch is connected between 12v in and 12v out . 12v out must exceed 11.1v before the pwrgd pin can pull low. a 440 w active pull-down discharges 12v out to ground when the power switches are turned off.
10 ltc4244/LTC4244-1 42441f block diagra w C + C + C + C + + C + C + C 5v out timer_lo 3 50mv timer_hi 3 150mv cp_off v cc 67 a 60 a 3.3v in 5v in 3.3v sense 5v sense gate 50mv + C + C + C 3.3v out timer_lo 3 50mv timer_hi 3 150mv 50mv 5v current fault v eein ref 3.3v current fault 13 off/on 14 15 16 17 fault drive sq r timer cp_off thermal fault cp_off cp_off thermal fault v ee current fault 12v current fault v cc 21 a cp_off v cc 12v in v cc thermal fault timer_lo timer_hi timer_hi q sq rq thermal fault 5v current fault 3.3v current fault v ee current fault 12v current fault 4 6 gnd 8 8 s rising edge delay 46 s falling edge delay 25 s rising edge delay 14 s falling edge delay 12v switch control charge pump v ee switch control thermal shutdown v cc ref reference uvl monitor reset v cc uvl 5 pwrgd 7 resetin 9 12v in 1 v eein 2 resetout 10 C + 4r 5v in r 11 precharge 12 12v out 20 5v out 3 3.3v out 18 v eeout 4244 bd 19 power good monitor ref cp_off v cc
11 ltc4244/LTC4244-1 42441f applicatio s i for atio wu uu hot circuit insertion when a circuit board is inserted into a live compactpci (cpci) bus, the supply bypass capacitors can draw huge inrush currents from the cpci power bus as they charge up. these transient currents can create glitches on the power bus, causing other boards in the system to reset. the ltc4244 is designed to turn a boards back-end supply voltages on and off in a controlled manner, allow- ing the board to be safely inserted or removed from a live cpci connector without glitching the system power sup- plies. it also protects the system supplies from shorts, precharges the bus i/o connector pins during hot insertion and extraction, and monitors the supply voltages. the ltc4244 is specifically designed for cpci applica- tions where the hot swap controller resides on the plug- in board. ltc4244 feature summary ? allows safe insertion and removal from a cpci back- plane. ? controls all four cpci supplies: -12v, 12v, 3.3v and 5v. ? adjustable foldback current limit for the 5v and 3.3v supplies: an adjustable analog current limit with a value that depends on the output voltage. if the output is shorted to ground the current limit drops to keep power dissipation and supply glitches to a minimum. ? 12v and C12v circuit breakers: if either supply remains in analog foldback current limit for more than 25 m s, the circuit breakers will trip, the supplies are turned off and the fault pin is pulled low. ? adjustable 5v and 3.3v circuit breakers: if either supply exceeds its current limit for more than 25 m s, the circuit breaker will trip, the supplies will be turned off and the fault pin is asserted low. in the event of a short circuit on either supply, an analog current limit will prevent the supply current from exceeding three times the circuit breaker threshold current. ? current limit during power up: the supplies are allowed to power up in current limit. this allows the ltc4244 to power up boards with widely varying capacitive loads without tripping the circuit breaker. the maximum allowable power-up time is adjustable using the timer pin capacitor. ? internal 12v and C12v power switches. ? pwrgd output: monitors the voltage status of the four back-end supply voltages. ? pci_rst# combined on chip with healthy# to create local_pci_rst# output. simply connect the pci_rst# signal to the resetin pin and the local_pci_rst# signal to the open-drain resetout pin. ? precharge output: on-chip reference and error amplifier provide 1v for biasing bus i/o connector pins during cpci card insertion and extraction. ? timer/aux. v cc : after power-up, the timer pin ca- pacitor serves as auxiliary v cc , thus enabling the ltc4244 to ride out large voltage spikes on the 12v in supply without interruption. ? undervoltage lockout: all four input voltages are pro- tected by undervoltage lockouts. ? space saving 20-pin ssop package. ltc4244 vs ltc1644 the ltc4244 is pin-for-pin compatible with the ltc1644. there are, however, some important differences between the two parts: ? timer: the ltc4244s timer pin threshold voltage is 1.6v below v 12vin vs 1v for the ltc1644. after power- up, the ltc4244s timer pin also doubles as auxiliary v cc . ?v eein uvl: the ltc4244 has a C9.5v uvl threshold protecting the v eein supply. the ltc1644 has no v eein uvl feature.
12 ltc4244/LTC4244-1 42441f ?5v in uvl threshold voltage: the ltc4244s 5v in uvl threshold voltage is 4.25v vs. 2.5v for the ltc1644. ?v eeout pwrgd threshold voltage: the ltc4244 v eeout power good threshold voltage is C11.1v vs C10.5v for the ltc1644. ? absolute maximum ratings: the ltc4244s absolute maximum ratings for the 12v in and v eein pins are 14.4v, respectively, vs 13.2v for the ltc1644. ? 5v/3.3v circuit breakers: if a short-circuit occurs after power-up, the ltc4244 actively limits the voltage dropped across the external 5v and 3.3v sense resis- tors to 150mv for 25 m s before tripping the circuit breaker. in the event either the 5v or 3.3v sense resistor voltage exceeds 150mv, the ltc1644 trips the circuit breaker without delay. ? 5v/3.3v circuit breaker threshold voltage: the ltc4244 threshold voltage is 52mv 5mv vs 55mv 15mv for the ltc1644. ? external gate voltage: after power-up, the voltage drop from the 12v in pin to the gate pin is 0.6v for the ltc4244 vs 50mv for the ltc1644. hot plug power-up sequence the ltc4244 is specifically designed for hot plugging cpci boards. the typical application circuit is shown in figure 1. cpci connector pin sequence the staggered lengths of the cpci male connector pins ensure that all power supplies are physically connected to the ltc4244 before back-end power is allowed to ramp up (bd_sel# asserted low). the long pins, which include 5v, 3.3.v, v(i/o) and gnd, mate first. the short bd_sel# pin mates last. at least one long 5v power pin must be connected to the ltc4244 in order for the precharge voltage to be available during the insertion sequence. the following is a typical hot insertion sequence: 1. esd clips make contact. 2. long power and ground pins make contact and early power is established. the 1v precharge voltage be- comes valid at this stage of insertion. power is also applied to the pull-up resistors connected to the fault, pwrgd and off/on pins. all power switches are held off at this stage of insertion. 3. medium length pins make contact. both fault and pwrgd continue to be pulled up high at this stage in the hot plug sequence, and the power switches are still held off. the 12v and C12v connector pins also make contact at this stage. zener clamps z1 and z2 plus shunt rc snubbers r16-c5 and r15-c4 help protect the v eein and 12v in pins, respectively, from large voltage tran- sients during hot insertion. the signal pins also connect at this point. these include the healthy# signal (which is connected to the pwrgd pin), the pci_rst# signal (which is connected to the resetin pin) and the i/o connector pins (which are biased at 1v by the ltc4244s precharge circuit). 4. short pins make contact. the bd_sel# signal is con- nected to the off/on pin. if the bd_sel# signal is grounded on the backplane, the plug-in card power-up cycle begins immediately. system backplanes that do not ground the bd_sel# signal will instead have cir- cuitry that detects when bd_sel# makes contact with the plug-in board. the system logic can then control the power up process by pulling bd_sel# low. power-up sequence the back-end 3.3v out and 5v out power planes are iso- lated from the 3.3v in and 5v in power planes by external n-channel pass transistors q1 and q2, respectively. inter- nal pass transistors isolate the back-end 12v out and v eeout power planes from the 12v in and v eein power planes. applicatio s i for atio wu uu
13 ltc4244/LTC4244-1 42441f sense resistors r1 and r2 provide current fault detection and r5 and c1 provide current control loop compensation as well as ramp rate control for the gate pin voltage. resistors r3 and r4 prevent high frequency oscillations in mosfets q1 and q2. a power-up sequence begins when the off/on pin is pulled low (figure 2). this enables the pass transistors to turn on and an internal 21 m a current source is connected to timer. once the pass transistors begin to conduct current, the supplies will start to power up. current limit faults are ignored while the timer pin voltage is ramping up and is less than (12v in C 1.6v). when all four supply voltages are within tolerance, healthy# will pull low and local_pci_rst# is free to follow pci_rst#. power-down sequence when the bd_sel# signal is pulled high, a power-down sequence begins (figure 3). internal switches are connected to each of the output voltage supply pins to discharge the bypass capacitors to ground. the timer pin is immediately pulled low. the gate pin is pulled down by a 60 m a current source to prevent the load currents on the 3.3v and 5v supplies from going to zero instantaneously and glitching the power supply voltages. when any of the output voltages dips below its threshold, the healthy# signal pulls high and local_pci_rst# will be asserted low. applicatio s i for atio wu uu timer 10v/div gate 10v/div 12v out 10v/div 5v out 10v/div 3.3v out 10v/div v eeout 10v/div bd_sel# 10v/div healthy# 10v/div lcl_pci_rst# 10v/div 10ms/div 4244 f02 figure 2. normal power-up sequence timer 10v/div gate 10v/div 12v out 10v/div 5v out 10v/div 3.3v out 10v/div v eeout 10v/div bd_sel# 10v/div healthy# 10v/div lcl_pci_rst# 10v/div 20ms/div 4244 f03 figure 3. normal power-down sequence
14 ltc4244/LTC4244-1 42441f once the power-down sequence is complete, the cpci card may be removed from the slot. during extraction, the precharge circuit continues to bias the bus i/o connector pins at 1v until the long 5v and 3.3v connector pin connections are broken. gate pin capacitor selection both the load capacitance and the ltc4244s gate pin capacitor (c1 in figure 1) affect the ramp rate of the 5v out and 3.3v out voltages. the precise relationship can be expressed as: dv or = i or = i out limit(5v) limit(3.3v) dt i c i c i c gate load v load vout load v load vout = 1 5 5 33 33 () () (. ) (. ) (1) whichever is slowest. the power-up time for any of the ltc4244s outputs where the inrush current is constrained by that supplys foldback current limit can be approxi- mated as: t cv ii on vout load out limit vout load vout () () () n nn n < 2 (2) where n v out = 5v out , 3.3v out , 12v out or v eeout . for example, if c load =2000 m f, i limit(5vout) = 6a and i load(5vout) = 5a, the 5v out turn-on time will be less than 20ms. if the value of c1 is large enough that it alone determines the output voltage ramp rate, then the magnitude of the inrush current initially charging the load capacitance is: i c c i inrush load gate = 1 (3) the maximum power-up time for this condition can be approximated by: t v v c max i on out th mosfet max gate min < + () ,() () ( ) 1 (4) where v th,mosfet(max) is the maximum threshold voltage of the external 5v or 3.3v mosfet. in general, the edge rate (di/dt) at which the back-end 5v and 3.3v supply currents are turned on can be limited by increasing the size of c1. applications that are sensitive to the edge rate should characterize how varying the size of c1 reduces di/dt for the external mosfet selected for a particular design. in the event of a short-circuit or overcurrent condition, the ltc4244s gate pin can be pulled down within 2 m s since a 1k w (r5 in figure 1) decouples c1 from the gates of the external mosfets (q1 and q2 in figure 1). timer pin capacitor selection during a power-up sequence, a 21 m a current source is connected to the timer pin and current limit faults are ignored until the voltage ramps to within 1.6v of 12v in . this feature allows the part to power up large capacitive loads using its foldback current limit. the timer inhibit period can be expressed as: t cvv i timer timer in timer timer = () 12 (5) the timer period should be set longer than the duration of any inrush current that exceeds the ltc4244s foldback current limit but yet be short enough not to exceed the maximum, safe operating area of the external 5v and 3.3v pass transistors in the event of a short circuit (see design example). as a design aid, the timer period as a function of the timing capacitor using standard values from 0.1 m f to 0.82 m f is shown in table 1. applicatio s i for atio wu uu
15 ltc4244/LTC4244-1 42441f table 1. t timer vs c timer c timer ( 10%) t timer(min) t timer(max) 0.1 m f 35ms 74ms 0.22 m f 77ms 162ms 0.33 m f 115ms 243ms 0.47 m f 164ms 346ms 0.68 m f 238ms 500ms 0.82 m f 287ms 603ms the timer pin is immediately pulled low when the bd_sel# pin signal goes high. thermal shutdown the internal switches for the 12v and C12v supplies are protected by a thermal shutdown circuit. when the junc- tion temperature of the die reaches 150 c, all switches will be latched off and the fault pin will be pulled low. short-circuit protection during a normal power-up sequence, if the timer pin is done ramping and any supply is still in current limit all of the pass transistors will be immediately turned off and fault will be pulled low as shown in figure 4. in order to prevent excessive power dissipation in the pass transistors and prevent voltage spikes on the supplies during short-circuit conditions, the current limit on each supply is designed to be a function of the output voltage. as the output voltage drops, the current limit decreases. unlike a traditional circuit breaker function where large currents can flow before the breaker trips, the current foldback feature guarantees that the supply current will be kept at a safe level. if either the 12v or C12v supply exceeds current limit after power-up, the shorted supplys current will drop applicatio s i for atio wu uu timer 10v/div gate 10v/div 3.3v out 10v/div bd_sel# 10v/div healthy# 10v/div fault 10v/div lcl_pci_rst# 10v/div 20ms/div 4244 f04 12v out 10v/div v eeout 10v/div 5v out 10v/div figure 4. power-up into a short on a 3.3v output
16 ltc4244/LTC4244-1 42441f immediately to its i limit value. if that supply remains in current limit for more than 25 m s, all of the supplies will be latched off. the 25 m s prevents quick current spikesfor example, from a fan turning onfrom causing false trips of the circuit breaker. after power-up, the 5v and 3.3v supplies are protected from short circuits by dual-level circuit breakers. in the event that either supplys current exceeds the nominal current limit, an internal timer is started. if the supply is still overcurrent after 25 m s, the circuit breaker trips and all the supplies are turned off (figure 5). an analog current limit loop prevents the supply current from exceeding 3 the nominal current limit in the event of a short circuit (figure 6). the ltc4244 will stay in the latched off state until the off/on pin is cycled high then low or the 12v in power supply is cycled low then high. the current limit and the foldback current level for the 5v and 3.3v outputs are both a function of the external sense resistor. as shown in figure 1, a sense resistor is con- nected between 5v in and 5v sense for the 5v supply. for the 3.3v supply, a sense resistor is connected between 3.3v in and 3.3v sense . the typical current limit and the foldback current levels are given by equations 6 and 7: i mv r limit vout sense vout () () n n = 51 (6) i mv r foldback vout sense vout () () n n = 16 (7) where n v out = 5v out or 3.3v out . the current limit for the internal 12v switch is set at 850ma folding back to 360ma and the C12v switch at 610ma folding back to 225ma. applicatio s i for atio wu uu gate 20v/div 5v out 10v/div fault 5v/div timer 20v/div 5v in C 5v sense 100mv/div 10 s/div 4244 f05 figure 5. overcurrent fault on 5v output gate 20v/div 3.3v out 5v/div fault 5v/div timer 20v/div 3v in C 3v sense 500mv/div 10 s/div 4244 f06 figure 6. short-circuit fault on 3.3v output
17 ltc4244/LTC4244-1 42441f calculating r sense determining the most appropriate value for the sense resistor first requires knowing the maximum current needed by the load under worst-case conditions. two other pa- rameters affect the value of the sense resistor. first is the tolerance of the ltc4244s circuit breaker threshold volt- age. the ltc4244s nominal circuit breaker threshold voltage is v cb(nom) = 52mv; however it exhibits 5mv tolerance over process and temperature. second is the tolerance (rtol) of the sense resistor. sense resistors are available in rtols of 1%, 2% and 5% and exhibit temperature coefficients of resistance (tcrs) between 75ppm/ c and 100ppm/ c. how the sense resistor changes as a function of temperature depends on the i 2 ? r power being dissipated by it. the power rating of the sense resistor should accommodate steady-state fault current levels so that the component is not damaged before the circuit breaker trips. table 2 lists i trip(min) and i trip(max) versus some sug- gested values of r sense . table 7 lists manufacturers and part numbers for these resistor values. table 2. i trip vs r sense r sense (1% rtol) i trip(min) i trip(max) 0.005 w 9.31a 11.5a 0.007 w 6.6a 8.2a 0.011 w 4.2a 5.2a output voltage monitor the status of all four output voltages is monitored by the power good function. in addition, the pci_rst# signal is logically combined on-chip with the healthy# signal to create local_pci_rst# (see table 3). as a result, local_pci_rst# will be pulled low whenever healthy# is pulled high independent of the state of the pci_rst# signal. if any of the output voltages drop below the power good threshold for more than 14 m s, the pwrgd pin will be pulled high and the local_pci_rst# signal will be asserted low. table 3. local_pci_rst# truth table pci_rst# healthy# local_pci_rst# lo lo lo lo hi lo hi lo hi hi hi lo precharge the precharge input and drive output pins are in- tended for use in generating the 1v precharge voltage that is used to bias the bus i/o connector pins during board insertion and extraction. the ltc4244 is also capable of generating precharge voltages other than 1v. figure 7 shows a circuit that can be used in applications requiring a precharge voltage of less than 1v. the circuit in figure 8 can be used for applications that need precharge voltages greater than 1v. precharge resistors are used to connect the 1v bias volt- age to the i/o lines with minimal disturbance. figure 1 shows the precharge application circuit for 5v signaling. the precharge resistor requirements are more stringent for 3.3v and universal hot swap boards. if the total leak- age current on the i/o line is less 2 m a, then a 50k resistor can be connected directly from the 1v bias voltage to the i/o line. however, many ics connected to the i/o lines can have leakage currents up to 10 m a. for these applications, a 10k resistor is used but must be disconnected when the board is seated as determined by the state of the bd_sel# signal. figure 9 shows a precharge circuit that uses a bus switch to connect the individual 10k precharge resistors to the ltc4244s 1v precharge pin. the electrical connec- tion is made (bus switches closed) when the voltage on the bd_sel# pin of the plug-in card is pulled-up to 5v in , which occurs just after the long pins have made contact. the bus switches are electrically disconnected when the short, bd_sel# connector pin makes contact and the applicatio s i for atio wu uu
18 ltc4244/LTC4244-1 42441f applicatio s i for atio wu uu figure 8. precharge voltage >1v application circuit q3 mmbt2222a 12 5% 3.3v in 4244 f08 1k 5% 18 5% r10b r10a precharge out *additional details omitted for clarity 4.7nf 11 12 8 r10a + r10b r10a v precharge = ? 1v drive precharge ltc4244* gnd figure 7. precharge voltage <1v application circuit q3 mmbt2222a 12 5% 3.3v in 4244 f07 1k 5% 18 5% r10b r10a precharge out *additional details omitted for clarity 4.7nf 11 12 8 r10a r10a + r10b v precharge = ? 1v drive precharge ltc4244* gnd 5v in c9 0.01 f per power pin 13 5 12 11 z4: smaj5.0a *additional details omitted for clarity data bus i/o 4244 f09 q3 mmbt2222a 8 r10 18 5% r19 1k 5% 3v in r13 10 5% r11 10k 5% r12 10k 5% precharge out 1v 10% i out = 55ma i/o r14 10 5% r22 2.7 r8 1k 5% r7 12 5% c3 4.7nf r9 24 pci bridge chip 5v long 5v bd_sel# ground i/o pin 1 i/o pin 128 ? ? ? ? ? ? ? ? ? z4 c7 0.01 f up to 128 i/o lines 0.1 f 100 q2 mmbt3906 r23 51.1k 5% r24 75k 5% bus switch v dd oe out out in pcb edge backplane connector backplane connector r20 1.2k 5% gnd 5v in off/on ltc4244* precharge drive figure 9. precharge bus switch application circuit for 3.3v and universal hot swap boards
19 ltc4244/LTC4244-1 42441f applicatio s i for atio wu uu bd_sel# voltage drops below 4.4v thus causing the bus switch oe to be pulled high by q2. the compactpci specification assumes that there is a diode to 3.3v on the circuit that is driving the bd_sel# pin. the 1.2k resistor pull-up to 5v in on the plug-in card will be clamped by the diode to 3.3v. if the bd_sel# pin is being driven high, the actual voltage on the pin will be approxi- mately 3.9v. this is still above the high ttl threshold of the ltc4244 off/on pin, but low enough for q2 to disable the bus switches and thus disconnect the 10k precharge resistors from the i/o lines. since the power to the bus switch is derived from a front-end power plane, a 100 w resistor should be placed in series with the power supply of the bus switch. when the plug-in card is removed from the connector, the bd_sel# connection is broken first, and the bd_sel# voltage pulls up to 5v in . this causes q2 to turn off, which re-enables the bus switch, and the precharge resistors are again connected to the ltc4244 precharge pin for the remainder of the extraction process. timer/auxiliary v cc once the timer pin voltage has ramped to within 1.6v of 12v in , the auxiliary v cc function is enabled. in the event the 12v in supply voltage collapses, the ltc4244 will continue to draw power from the charge stored on the timer pin capacitor until the internal v cc node drops below its undervoltage lockout threshold or the 12v in supply voltage recovers, whichever happens first. other compactpci applications the LTC4244-1 is designed for compactpci designs where the C12v supply is not being used on the plug-in board. the v eeout power good comparator, v eein uvl, and v ee circuit breaker functions are disabled. the v eein pin should be connected to gnd and the v eeout pin left floating if a C12v output is not needed. if no 3.3v supply input is required, figure 10 illustrates how the ltc4244 should be configured: 3.3v sense and 3.3v in are connected to 5v in and 3.3v out is connected to 5v out . for applications where the bd_sel# connector pin is typically connected to ground on the backplane, the circuit in figure 11 allows the ltc4244 to be reset simply by pressing a pushbutton switch on the cpci plug in board. this arrangement eliminates the requirement to extract and reinsert the cpci board in order to reset the ltc4244s circuit breaker. c1 0.33 f 5v in 13 17 16 18 3 15 14 8 r4 10 5v out 4244 f10 r5 1k r2 0.007 q2 irf7457 z4 z4: smaj5.0a *additional pins omitted for clarity pcb edge backplane connector backplane connector 5v long 5v ground gnd 5v in 5v sense 3.3v out 3.3v in ltc4244* 5v out 3.3v sense gate figure 10. no 3.3v supply application circuit 8 1.2k pushbutton switich 100 0.25w v(i/o) 1k ground 5 bd_sel# 4244 f11 *additional pins omitted for clarity pcb edge backplane connector backplane connector gnd ltc4244* off/on figure 11. bd_sel# pushbutton toggle switch
20 ltc4244/LTC4244-1 42441f power mosfet selection criteria the ltc4244 uses external mosfets to limit the 5v and 3.3v supply currents. the following criteria should be used when selecting these mosfets: 1. the on resistance should be low enough to prevent an excessive voltage drop across the sense resistor and the series mosfet at rated load current given the amount of gate to source voltage provided by the ltc4244. 2. the drain-to-source breakdown voltage should be high enough for the device to survive overvoltage transients that may occur during fault conditions (the 5v and 3.3v transient voltage limiters shown in figure 1 will limit the maximum drain-source voltage seen by these mosfets during fault conditions). 3. the mosfet package must be able to handle the maximum, steady state power dissipation for the on state without exceeding the devices rated maximum junction temperature. the mosfets steady-state, dis- sipated power can be expressed as: p on = i max 2 ? r ds(on) (8) the increase in steady-state junction-to-ambient tem- perature is given by: t j C t a = p on ? r q ja (9) 4. the mosfet package must be able to dissipate the heat resulting from the power pulse during the transition from off to on. a worst-case approximation for the magnitude of the power pulse is: p vi i out inrush load off-on < + () n 2 (10) where n v out = 5v out or 3.3v out , i inrush is the tran- sient current initially charging the load capacitance and i load is the steady-state load current. the duration, t on , of the power pulse can be expressed as: t cv i on load out inrush = (11) applicatio s i for atio wu uu 5. the mosfet package must be able to sustain the maximum pulse power that occurs in the event the ltc4244 attempts to power-up either the 5v or 3.3v back-end supply into a short circuit (see design ex- ample for a sample calculation). table 8 lists some power mosfets that can be used with the ltc4244. input overvoltage transient protection hot plugging a board into a backplane generates inrush currents from the backplane power supplies due to the charging of the plug-in board capacitance. to reduce this transient current to a safe level, the cpci hot swap specification restricts the amount of unswitched capaci- tance used on the input side of the plug-in board. each medium or long power pin connected to the cpci female connector on the plug-in board is required to have a 10nf ceramic bypass capacitor to ground. bulk capacitors are only allowed on the switched output side of the ltc4244 (5v out , 3.3v out , 12v out , v eeout ). some bulk capaci- tance is allowed on the 5v in and 3.3v in early power planes, but only because a current limiting resistor is assumed to decouple the connector pin from the bulk capacitance. circuits normally placed on the unswitched side early power plane (pci bridge, for example) need to to be decoupled by a current limiting resistor. disallowing bulk capacitors on the input power pins miti- gates the inrush current during hot swap. however, it also tends to create a resonant circuit formed by the inductance of the backplane power supply trace in series with the inductance of the connector pin and the parasitic capaci- tance of the plug-in board (mainly due to the large power fet). upon board insertion, the ringing of this circuit can exhibit a peak overshoot of 2.5 times the steady-state voltage (>30v for 12v in ). there are two methods for abating the effects of these high voltage transients: using voltage limiters to clip the tran- sient to a safe level and snubber networks. snubber networks are series rc networks whose time constants
21 ltc4244/LTC4244-1 42441f are experimentally determined based on the boards para- sitic resonance circuits. as a starting point, the capacitors in these networks are chosen to be 10 to 100 the power mosfets c oss under bias. the series resistor is a value determined experimentally that ranges from 1 w to 50 w , depending on the parasitic resonance circuit. note that in all ltc4244 circuit schematics, both transient voltage limiters and snubber networks have been added to the 12v in and v eein supply rails and should always be used. snubber networks are not necessary on the 3.3v in or the 5v in supply lines since their absolute maximum voltage ratings are 13.5v. transient voltage limiters, however, are recommended as these devices provide large-scale tran- sient protection for the ltc4244 in the event of abrupt changes in supply current. all protection networks should be mounted very close to the ltc4244s supply pins using short lead lengths to minimize trace resistance and induc- tance. this is shown schematically in figures 12 and 13 and a recommended layout of the transient protection devices around the ltc4244 is shown in figure 14. applicatio s i for atio wu uu c1 0.047 f 3.3v in 3v in 3.3v 5v in 5v 3.3v sense 17 3.3v out 18 5v in 13 5v out 3 5v sense 14 16 gate 15 r3 10 r4 10 5v out 5v 3v out 3.3v r5 1k r1 0.005 q1 irf7457 q2 irf7457 r2 0.007 z3 z4 ltc4244* 4244 f12 gnd 8 z3, z4: smaj5.0a *additional details omitted for clarity figure 12. place transient protection devices close to ltc4244s 5v in and 3.3v in pins 12v in 1 v eein 12v in C12v in 2 z1 z2 r14 10 c5 0.1 f ltc4244* 4244 f16 gnd 8 z1, z2: smaj12ca *additional details omitted for clarity r13 10 c4 0.1 f 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 vias to gnd plane c4 r13 gnd 5v in ltc4244* *additional details omitted for clarity drawing is not to scale! 4244 f14 3.3v in v eein 12v in c5 r14 z4 z1 z1 z3 figure 13. place transient protection devices close to ltc4244s 12v in and v eein pins figure 14. recommended layout for transient protection components
22 ltc4244/LTC4244-1 42441f pcb layout considerations for proper operation of the ltc4244s circuit breaker, 4-wire kelvin sense connections between the sense resis- tor and the ltc4244s 5v in and 5v sense pins and 3.3v in and 3.3v sense pins are strongly recommended. the pcb layout should be balanced and symmetrical to minimize wiring errors. in addition, the pcb layout for the sense resistors and the power mosfets should include good thermal management techniques for optimal device power dissipation. a recommended pcb layout for the sense resistor, the power mosfet and the gate drive compo- nents around the ltc4244 is illustrated in figure 15. in hot applicatio s i for atio wu uu swap applications where load currents can be 10a, nar- row pcb tracks exhibit more resistance than wider tracks and operate at more elevated temperatures. since the sheet resistance of 1 ounce copper foil is approximately 0.45m w / o , track resistance and voltage drops add up quickly in high current applications. thus, to keep pcb track resistance, voltage drop and temperature to a mini- mum, the suggested trace width in these applications for 1 ounce copper foil is 0.03 for each ampere of dc current. in the majority of applications, it will be necessary to use plated-through vias to make circuit connections from component layers to power and ground layers internal to 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 ltc4244* current flow to source *additional details omitted for clarity drawing is not to scale! 4244 f15 track width w: 0.03" per ampere on 1 oz cu foil d d d d g s s s current flow to load current flow to load sense resistor so-8 via to gnd plane gnd gnd 3.3v out 3.3v 3.3v in 3.3v via/path to gnd gate r3 r5 c1 c timer w w w figure 15. recommended layout for power mosfet, sense resistor and gate components for the 3.3v rail
23 ltc4244/LTC4244-1 42441f the pc board. for 1 ounce copper foil plating, a general rule is 1 ampere of dc current per via making sure the via is properly dimensioned so that solder completely fills the void. for other plating thicknesses, check with your pcb fabrication facility. design example as a design example, consider a cpci hot swap applica- tion with the following power supply requirements: table 4. design example power supply requirements voltage maximum dc load supply supply current capacitance 12v 450ma 100 m f 5v 5a 2200 m f 3.3v 7a 2200 m f C12v 100ma 100 m f the first step is to select the appropriate values of r sense for the 5v and 3.3v supplies. calculating the value of r sense is based on i load(max) and the lower limit for the circuit breaker threshold voltage (47mv for both the 5v and 3.3v circuit breakers). if a 1% tolerance is assumed for the sense resistors, then 5m w and 7m w resistor values yield the following minimum and maximum i trip values: table 5. i trip vs r sense r sense (1% rtol) i trip(min) i trip(max) 5m w 9.3a 11.5a 7m w 6.6a 8.2a so sense resistor values of 7m w and 5m w should suffice for the 5v and 3.3v supplies, respectively. the second step is to select mosfets for the 5v and 3.3v supplies. the irf7457s on resistance is less than 10.5m w for v gs > 4.5v and a junction temperature of 25 c. since the maximum load current requirement for the 3.3v sup- ply is 7a, the steady-state power the device may be required to dissipate is 514mw. the irf7457 has a junction-to-ambient thermal resistance of 50 c/watt. if a maximum ambient temperature of 50 c is assumed, this yields a junction temperature of 75.7 c. according to the irf7457s normalized on-resistance vs junction tem- perature curve, the devices on-resistance can be expected to increase by about 20% over its room temperature value. recalculation of the steady-state values of r on and junc- tion temperature yields approximately 12.6m w and 81 c, respectively. the i ? r drop across the 3.3v sense resistor and series mosfet at maximum load current under these conditions will be less than 124mv. the next step is to select appropriate values for c1 and c timer . assuming that the total current for the 5v supply is constrained to less than 6a during power-up (6 5v medium length connector pins at 1a per pin), then the inrush current shouldnt exceed: i inrush < 6a C i load(5vout) = 6a C 5a = 1a (12) this yields: c if i c af a nf gate max inrush max 1 2200 1 100 2200 1 220 > m t> mm = () () (13) hence a c1 value of 330nf 10% should suffice. the value of c timer for this design example will be constrained by the duration of the 12v supply inrush current, which according to equation 2 is: t cv ii t fv ma ma ms on vout load limit min load max on vout () () ( ) () 12 12 212 2 100 12 550 450 24 < t< m = (14) in order to guarantee that the ltc4244s timer fault inhibit period is greater than 24ms, the value of c timer should be: c ms i vv c ms a vv nf timer timer max timer max timer > t> m = 24 12 24 26 12 1 9 61 8 . . () () (15) so a value of 82nf ( 10%) should suffice. applicatio s i for atio wu uu
24 ltc4244/LTC4244-1 42441f output voltage (v) 0 dissipated power (w) 15 20 25 4 4244 f16 10 5 0 1 2 3 5 5v mosfet 5v r sense = 0.007 3.3v r sense = 0.005 3.3v mosfet figure 16. worst-case 5v and 3.3v mosfet dissipated power vs output voltage the next step is to verify that the thermal ratings of the external 5v and 3.3v mosfets arent being exceeded during power-up cycles into the designed loads or into a short circuit. the amount of heating in the 5v and 3.3v mosfets during a normal power cycle depends on the ltc4244s gate pin current (refer to gate current vs temperature plot in the typical performance characteristics section). the magni- tude of the off-on power pulse that results in maximum heating of the mosfets is given by equation 10 as: p vi i out inrush min load vout off-on = + () n n () ( ) 2 (16) where i c c max i inrush min load gate min () () () = 1 (17) the duration of the power-pulse is given by equation 11 as: t cv i inrush load out inrush min < () n (18) solving these equations for the 5v and 3.3v supplies yields: table 6 p off-on t inrush(max) 5v mosfet 12.8w 90ms 3.3v mosfet 11.8w 60ms under these conditions, the irf7457 datasheets thermal response vs pulse duration curve indicates that the junction-to-ambient temperature will increase by 60 c for the 5v mosfet and 46 c for the 3.3v mosfet. the duration and magnitude of the power pulse that results during a short-circuit condition on either the 5v or 3.3v outputs are a function of the timer capacitor and the ltc4244s foldback current limit. figure 16 shows the worst-case power dissipated in the 5v and 3.3v external fets vs v 5vout and v 3.3vout , respectively. in the case of the 3.3v external mosfet, the maximum dissipated power is 24 watts (v 3.3vout = 0.9v). for the 5v external mosfet, the maximum dissipated power is 22 watts (v 5vout = 1.75v). the maximum duration of the short-circuit power- pulse is given by equation 19 as: tc vv i t nf nf v v a tms pulse timer max timer min timer min pulse pulse < t< + ()() m t< () () () . . . 12 82 8 2 12 1 3 16 60 3 (19) applicatio s i for atio wu uu
25 ltc4244/LTC4244-1 42441f the irf7457s thermal response vs pulse duration curve indicates that the worst-case increase in junction-to- ambient temperature during a power-cycle for the 3.3v mosfet is less than 96 c while the worst-case increase in junction-to-ambient temperature for the 5v mosfet is less than 88 c. power mosfet and sense resistor selection tables 7 and 8 list current sense resistors and power mosfet transistors, respectively, that can be used with the ltc4244s circuit breakers. table 9 lists supplier web site addresses for discrete components mentioned throughout the ltc4244 data sheet. obtaining information on specific parts for more information or to request a copy of the compactpci specification, contact the pci industrial com- puter manufacturers group at: pci industrial computer manufacturers group wakefield, ma 01880 usa phone: 01 (718) 224-1239 web site: http://www.picmg.com transient voltage suppressors smaj12a and smaj5.0a are supplied by: diodes, incorporated westlake village, ca 91362 usa phone: 01 (805) 446-4800 web site: http://www.vishay.com or http://www.diodes.com transistors mmbt2222a and mmbt3906 are supplied by: on semiconductor phoenix, az 85008 usa phone: 01 (602) 244-6600 web site: http://www.onsemi.com applicatio s i for atio wu uu
26 ltc4244/LTC4244-1 42441f applicatio s i for atio wu uu table 7. sense resistor selection guide current limit value part number description manufacturer 1a lr120601r055f 0.055 w , 0.5w, 1% resistor irc-tt wsl1206r055 vishay dale 2a lr120601r028f 0.028 w , 0.5w, 1% resistor irc-tt wsl1206r028 vishay dale 5a lr120601r011f 0.011 w , 0.5w, 1% resistor irc-tt wsl2010r011 vishay dale 7.6a wsl2512r007 0.007 w , 1w, 1% resistor vishay dale 10a wsl2512r005 0.005 w , 1w, 1% resistor vishay dale table 8. n-channel power mosfet selection guide current limit value part number description manufacturer 0a to 2a mmdf3n02hd dual n-channel so-8, r ds(on) = 0.1 w on semiconductor 2a to 5a mmsf5n02hd single n-channel so-8, r ds(on) = 0.025 w on semiconductor 5a to 10a mtb50n06v single n-channel dd-pak, r ds(on) = 0.028 w on semiconductor 5a to 10a irf7457 single n-channel so-8, r ds(on) = 0.007 w international rectifier 5a to 10a si7880dp single n-channel powerpak tm , r ds(on) = 0.003 w vishay siliconix powerpak is a trademark of vishay siliconix table 9. manufacturers web site manufacturer web site international rectifier www.irf.com on semiconductor www.onsemi.com irc-tt www.irctt.com vishay dale www.vishay.com vishay siliconix www.vishay.com diodes, inc. www.diodes.com
27 ltc4244/LTC4244-1 42441f u package descriptio gn package 20-lead plastic ssop (narrow .150 inch) (reference ltc dwg # 05-08-1641) .337 ?.344* (8.560 ?8.738) gn20 (ssop) 0204 12 3 4 5 6 7 8910 .229 ?.244 (5.817 ?6.198) .150 ?.157** (3.810 ?3.988) 16 17 18 19 20 15 14 13 12 11 .016 ?.050 (0.406 ?1.270) .015 .004 (0.38 0.10) 45 0 ?8 typ .0075 ?.0098 (0.19 ?0.25) .0532 ?.0688 (1.35 ?1.75) .008 ?.012 (0.203 ?0.305) typ .004 ?.0098 (0.102 ?0.249) .0250 (0.635) bsc .058 (1.473) ref .254 min recommended solder pad layout .150 ?.165 .0250 bsc .0165 .0015 .045 .005 *dimension does not include mold flash. mold flash shall not exceed 0.006" (0.152mm) per side **dimension does not include interlead flash. interlead flash shall not exceed 0.010" (0.254mm) per side inches (millimeters) note: 1. controlling dimension: inches 2. dimensions are in 3. drawing not to scale information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
28 ltc4244/LTC4244-1 42441f part number description comments ltc1421 hot swap controller dual supplies from 3v to 12v, additional C12v ltc1422 hot swap controller single supply hot swap in so-8 from 3v to 12v lt1640al/lt1640ah negative voltage hot swap controllers in so-8 negative high voltage supplies from C10v to C80v lt1641-1/lt1641-2 positive voltage hot swap controllers in so-8 supplies from 9v to 80v, latch off/autoretry ltc1642 fault protected hot swap controller 3v to 15v, overvoltage protection up to 33v ltc1643al/ltc1643al-1 pci bus hot swap controllers 3.3v, 5v, 12v, C12v supplies for pci bus ltc1643ah ltc1644 compact pci bus hot swap controller 3.3v, 5v, 12v, local reset logic and precharge ltc1645 2-channel hot swap controller operates from 1.2v to 12v, power sequencing ltc1646 dual compactpci hot swap controller 3.3v, 5v supplies only ltc1647 dual hot swap controller dual on pins for supplies from 3v to 15v ltc4211 hot swap controller with multifunction current control single supply, 2.5v to 16.5v, msop ltc4240 compactpci hot swap controller i 2 c interface allows control and readback of device functions lt4250 C48v hot swap controller in so-8 C20v to C80v, active current limiting ltc4251 C48v hot swap controller in sot-23 floating supply, active current limiting and fast circuit breaker lt/tp 0204 1k ? printed in usa ? linear technology corporation 2003 linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 l fax: (408) 434-0507 l www.linear.com related parts typical applicatio u 3.3v in 12v in 12v out v eein off/on z4 5v in r4 10 c load(5vout) v out 5v 5a v out 3.3v 7a r5 1k c1 0.33 f r3 10 r1 0.005 r2 0.007 q1 irf7457 q2 irf7457 3.3v out 3.3v sense gnd precharge 5v in 5v sense drive r9 24 1v 10% q3 mmbt2222a c3 4.7nf v in 3.3v 4244 f17 LTC4244-1 gate 5v out + c load(3.3vout) + v out 12v 500ma c load(12vout) + v eeout timer resetout i/o #1 i/o #128 v out 3.3v c2 0.082 f z3 z2 r17 10k 3.3v in r22 2.7 c9 0.01 f per power pin c7 0.01 f c8 0.01 f per power pin r21 1.8 r19 1k fault pwrgd resetin r18 10k r20 1.2k r8 1k r7 12 r6 10k r10 18 r11 10k r13 10 r14 10 ? ? ? ? ? ? ? ? ? r12 10k r15 1 c4 0.01 f i/o data line 1 i/o data line 128 z1, z2: smaj12a z3, z4: smaj5.0a i/o pin 128 reset# pci bridge chip i/o pin 1 ground pci_rst# local_pci_rst# healthy# long v(i/o) bd_sel# 12v long 3.3v long 5v 3.3v 5v figure 17. typical LTC4244-1 application

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